In RF communications is often useful to be able to measure the power available at an output of the RF power amplifier. In order to measure the power of signals being transmitted, a power detector is implemented along the signal path in the RF power amplifier. In a typical multistage amplifier, a power detector may be located at the final stage and is usually coupled to the collector or base of the final stage amplifying transistor.
The simplest known power detector is a diode junction which is coupled along the signal path. This diode is commonly forward biased to improve dynamic range by pulling the diode closer to its turn on voltage. The approach of using a single diode is not often taken because it loads the RF source, and all of the energy produced at the DC output of the power detector comes from the RF signal and hence reduces the RF signal strength.
In order to present higher impedance to the RF source and hence cause minimal power reduction in the RF signal, the most commonly used power detector is a transistor in an emitter follower power detector configuration. In this well-known power detector, the base of the transistor is pulled to a voltage that turns the transistor on slightly, resulting in, for example, 300 mV on the emitter, the base is coupled to receive the RF signal, while the collector is coupled to a constant voltage source for example VCC. In response to a varying RF signal, the emitter follower acts as a rectifier, the emitter rising above ground during positive RF swings and the emitter dropping only marginally below ground on negative RF swings. This power detector configuration not only presents a “light” load to the RF amplifier, it does so while maintaining low output impedance. The energy produced at the DC output of this power detector comes from the constant voltage source and not from the RF signal.
As discussed above, a power detector is often coupled to the collector or base of the transistor of the final stage of the power amplifier. There are advantages and disadvantages to each alternative.
If the power detector is connected at the collector of the transistor of the final stage, the power detector will advantageously be presented with a large voltage swing, however, the frequency response of the power detector would be quite poor because the collector is presented with a load that is substantially reactive leading to an uneven frequency response. This can be alleviated somewhat by employing a matching network between the tap point and the power detector, however, the power detector presents such a high impedance load that the size of the required inductors is prohibitive for high frequency applications, such as applications involving the 2-5 GHz band.
Power detectors utilized in association with amplifiers used for WiLAN front end modules are often connected to the base input of the transistor of the last stage of amplification. In this case, the power detector will advantageously be isolated from changes in impedance presented to the output of the power amplifier, however, due to the relatively low voltage swing at the base of the transistor of the last stage of amplification, the DC voltage from the power detector will consequently be relatively weak. Due to the poor frequency response which would result from the placement of the power detector at the collector as described above, this approach of coupling at the base is more commonly used.
A well known approach used to compensate for the relatively weak signal output from the power detector when connected to the base of the transistor of the last stage of amplification, is the employment of a voltage doubler to double the voltage provided from the power detector output. Typical voltage doublers are based on diodes and they present a load to the RF stage driving it.
FIG. 1a illustrates a typical voltage doubling power detector according to the prior art. The power detector generally indicated by 100a has an RF input port RFIN which is coupled with a series first capacitor 110 to a cathode of a first diode 120. The cathode of the first diode 120 is also coupled to an anode of a second diode 130. An anode of the first diode 120 is coupled to ground. A cathode of the second diode 130 is coupled to a second capacitor 140 to ground, to a resistor 150 to ground, and is coupled to an output DCOUT of the power detector 100a. 
The RF input port RFIN of the power detector 100a receives a detected RF signal to be doubled. This typically originates along a signal path in the RF amplifier and is coupled to detect a voltage of the RF signal passing therethrough. During negative half-cycles of the RF signal the first diode 120 is forward biased into an ON state while the second diode 130 is reverse biased to an OFF state. During these negative half cycles capacitor 110 will be charged to a peak voltage of the RF signal. During positive half cycles, the first diode 120 is reverse biased into an OFF state while the second diode 130 is forward biased to an ON state. During these positive half cycles the second capacitor 140 is charged by the discharge of the first capacitor 110, and once enough cycles have occurred, the peak voltages presented to the output DCOUT of the power detector is roughly twice that of the peak voltage presented to the input RFIN of the power detector 100a. The resistor 150 along with the capacitor 140 define an RC time constant that suppresses the RF energy at DCOUT, and allows DC and baseband voltages to appear at DCOUT.
The prior art power detector 100a depicted in FIG. 1a has the drawback that each of the first and second diodes 120, 130 do not enter an ON state until the forward voltage exceeds a certain threshold which may be as high as between 0.7V-1.3V depending upon the semiconductor type. This forward voltage prevents the detector from responding to small RF signals.
In FIG. 1b is depicted a prior art power detector 100b which compensates for the threshold voltage which must be reached to cause the first and second diodes 120, 130 to enter the ON state. The power detector 100b of FIG. 1b is the same as the power detector 100a of FIG. 1a in every respect except that the first diode 180 of the power detector 100b is not connected to ground but instead is forward biased by a DC bias source 160. The voltage provided by the DC bias source 160 to the anode of first diode 180 is a voltage which is just below the threshold voltage for turning the first diode 180 and second diode 130 into the ON state. This causes the first diode 180 to be forward biased as soon as the RF signal begins to swing into negative voltages. Since the first diode 180 turns on earlier during the negative cycle, the first capacitor 110 charges to a higher voltage which in turn during the positive cycles charges the second capacitor 140 through the second diode 130 to a higher level providing an overall increase in dynamic range at the output DCOUT.
As described above, these prior art approaches present a substantial load to the RF signal passing through the RF amplifier and hence consumes a substantial amount of RF energy.
The invention provides for a solution which simultaneously mitigates multiple problems with prior art approaches such as low input impedance, high output impedance, low output signal, and uneven frequency response.